In recent years, in the field of telecommunication, the speeding up of data rate accompanying the increase in data traffic is progressing. Normally, a high-speed data signal is generated by processing a plurality of low-speed parallel data signals in a parallel-serial converter circuit (MUX).
FIG. 1 is a diagram illustrating a configuration example of a general parallel-serial converter circuit. Moreover, FIG. 2 illustrates a timing chart of signals processed by the circuit of FIG. 1.
The parallel-serial converter circuit illustrated in FIG. 1 serial-converts data signals Din0 and Din1 which are parallel-input to two input terminals IN0 and IN1, using a plurality of flip-flops 1-1, 1-2, 1-3, 1-4, and 1-5, and a selector 2, to thereby generate a data signal Dout having a twofold data rate, and outputs this data signal Dout from an output terminal OUT.
Specifically, one of the input data signals Din0 is latched sequentially by the cascade-connected three flip-flops 1-1, 1-2, and 1-3, and is then input as one selection data signal D0 to the selector 2. The other input data signal Din1 is latched sequentially by the cascade-connected two flip-flops 1-4 and 1-5, and is then input as another selection data signal D1 to the selector 2. The respective flip-flops 1-1 to 1-5 serving as latching circuits, operate in accordance with a clock signal CLKL having a frequency corresponding to the data rate of the input data signals Din0 and Din1. The flip-flops 1-2 and 1-5 execute a setup and a hold according to the rising edge of the clock signal CLKL, and the flip-flops 1-1, 1-3, and 1-4 execute a setup and a hold according to the falling edge of the clock signal CLKL.
Consequently, the input data signals Din0 and Din1 are taken into the flip-flops 1-1 and 1-4 according to the falling edge of the clock signal CLKL, and are sequentially sent to the next flip-flops 1-2, 1-3, and 1-5 in half a cycle of the clock signal CLKL. Then the selection data signal D0 which has passed the three flip-flops 1-1, 1-2, and 1-3, and the selection data signal D1 which has passed the two flip-flops 1-4 and 1-5 become signals having phases that are different from each other by 180°, as illustrated in the third and fourth stage of FIG. 2, and are input to the selector 2. In this way, the input timing of the selection data signals D0 and D1 with respect to the selector 2 is adjusted by the flip-flops 1-1 to 1-5, which operates according to the clock signal CLKL.
A clock signal CLKS having a frequency the same as that of the clock signal CLKL is supplied as a switching clock to the selector 2. The timing between the clock signal CLKL and the clock signal CLKS is adjusted by a buffer circuit B. The selector 2 switching-operates according to the clock signal CLKS, and alternately selects the selection data signal D0 and the selection data signal D1 to thereby output a serial-converted data signal Dout. Here, as illustrated in the third to fifth stage of FIG. 2, the selector 2 selects the selection data signal D1 according to the rising edge of the clock signal CLKS, and selects the selection data signal D0 according to the falling edge of the clock signal CLKS. Consequently, the data signal Dout output from the selector 2 to the output terminal OUT becomes a serial data signal having a data rate corresponding to the twofold frequency of the clock signal CLKS as illustrated in the sixth stage of FIG. 2.
The above parallel-serial converter circuit of FIG. 1 is of a configuration in which a single serial data signal is generated from two parallel data signals. However, with application of a multistage configuration which combines a plurality of conversion units with this circuit serving as a single conversion unit, it is possible to realize a parallel-serial converter circuit capable of handling multiple parallel data signals, in which one serial data signal is generated from four parallel data signals for example (for example, refer to Japanese Laid-open Patent Publication No. 2002-9629 and Japanese Laid-open Patent Publication No. 08-65173).
FIG. 3 is a functional block diagram illustrating an example of a parallel-serial converter circuit of a two-stage configuration capable of handling four parallel data signals. In this parallel-serial converter circuit, four input data signals Din are parallel-input to a first stage data conversion section 11 and serial-converted two at a time, and the data conversion section 11 outputs two data signals having a data rate twice that of each input data signal Din. Furthermore, the output data signals of the data conversion section 11 are parallel-input to a second stage data conversion section 12 and serial-converted, and the data conversion section 12 outputs a single data signal Dout having a data rate four times that of each input data signal Din.
In a parallel-serial converter circuit of the above two-stage configuration, the frequency of a clock signal CLK″ which drives the first stage data conversion section 11 is ½ of the frequency of the clock signal CLK′ which drives the second data conversion section 12. Therefore, the circuit configuration on the clock side is generally of a configuration in which for example: a clock signal CLK having a frequency corresponding to the data rate of a post-serial conversion data signal Dout is externally given; the frequency of this clock signal CLK is divided into ½ in a frequency dividing circuit 21 to thereby generate a clock signal CLK′; this clock signal CLK′ is sent to the second stage data conversion section 12; further, the frequency of the clock signal CLK′ is divided into ½ in a frequency divider circuit 22 to thereby generate a clock signal CLK″; and this clock signal CLK″ is sent to the first stage data conversion section 11.
Incidentally, as for a parallel-serial converter circuit to which the above configuration illustrated in FIG. 3 is applied, it is important that a data signal to be parallel-input to the data conversion section 12 of the latter stage, and a clock signal CLK′ to be given to this data conversion section 12 are synchronized. The timing of the data signal to be input to the data conversion section 12 is dependant on propagation delay, which occurs between the timing of the clock signal CLK″ given to the data conversion section 11 of the former stage and the moment at which the data signal output from this data conversion section 11 reaches the data conversion section 12 of the latter stage.
In the above configuration of FIG. 3, the propagation direction (the right to left direction in FIG. 3) of the clock signal on the frequency dividing circuits 21 and 22 side is opposite of the propagation direction (the left to right direction in FIG. 3) of the data signal on the data conversion sections 11 and 12 side. Therefore a differential delay (T1−T2) occurs between a propagation time T1 of a signal (clock signal CLK′) which propagates through a path P1 from the output of the frequency dividing circuit 21 to the data conversion section 12, and a propagation time T2 of signals (clock signals CLK′ and CLK″, and a data signal output from parallel-serial conversion) which propagate through a path P2 from the output of the frequency dividing circuit 21 through the frequency dividing circuit 21 and the data conversion section 11 to the data conversion section 12. If the absolute value of this differential delay is an integral multiple of a single cycle of the clock signal CLK′ given to the data conversion section 12, the data conversion section 12 is normally operated by the clock signal CLK′. Therefore, in a normal circuit design, the buffer circuit B serving as a delaying element is appropriately arranged on the propagation path of the respective clock signals CLK′ and CLK″ and on the propagation path of the data signal output from the data conversion section 11, and thereby the timing of the data signal and the clock signal CLK′ to be parallel-input to the data conversion section 12 is optimized.
However, the above differential delay varies, depending on variations in power supply voltage and temperature of the parallel-serial converter circuit, and on manufacturing variations of the circuit. Therefore, variations in this differential delay influence the operation of the respective data conversion sections 11 and 12. Specifically, regarding the operation of the respective data conversion sections 11 and 12, the allowable value of timing deviation of clock signals for operating the flip-flops and selectors, which constitute the respective data conversion sections, becomes smaller accompanying the speeding up of data signals to be processed. Therefore, in a case of handling high-speed data rate, there is a problem in that variations in differential delay which occur as a result of variations and the like in the abovementioned power supply voltage, cause the timing deviation of clock signals to exceed the allowable value, and consequently errors occur during the process of parallel-serial conversion.